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Low Complexity Design of Ripple Carry and Brent—Kung Adders in QCAPUDI, Vikramkumar; SRIDHARAN, K.IEEE transactions on nanotechnology. 2012, Vol 11, Num 1, pp 105-119, issn 1536-125X, 15 p.Article

New uniquely decodable codes for the T-user binary adder channel with 3 ≤ T ≤ 5KIVILUOTO, Lasse; ÖSTERGARD, Patric R. J.IEEE transactions on information theory. 2007, Vol 53, Num 3, pp 1219-1220, issn 0018-9448, 2 p.Article

Single SOA based all-optical adder assisted by optical bandpass filter : Theoretical analysis and performance optimizationJIANJI DONG; SONGNIAN FU; XINLIANG ZHANG et al.Optics communications. 2007, Vol 270, Num 2, pp 238-246, issn 0030-4018, 9 p.Article

Carry checking/parity prediction adders and ALUsNICOLAIDIS, Michael.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 1, pp 121-128, issn 1063-8210, 8 p.Article

A High-Reliability, Low-Power Magnetic Full AdderYI GANG; WEISHENG ZHAO; KLEIN, Jacques-Olivier et al.IEEE transactions on magnetics. 2011, Vol 47, Num 11, pp 4611-4616, issn 0018-9464, 6 p.Article

Accelerated two-level carry-skip adders : a type of very fast addersKANTABUTRA, V.IEEE transactions on computers. 1993, Vol 42, Num 11, pp 1389-1393, issn 0018-9340Article

MILLIMETER-WAVE POWER-COMBINING TECHNIQUESKAI CHANG; CHENG SUN.1983; IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES; ISSN 0018-9480; USA; DA. 1983; VOL. 31; NO 2; PP. 91-107; BIBL. 80 REF.Article

COMBINING THE POWERS FROM MULTIPLE-DEVICE OSCILLATORSMOHAMMAD MADIHIAN; MIZUSHINA S.1982; IEEE TRANS. MICROWAVE THEORY TECH.; ISSN 0018-9480; USA; DA. 1982; VOL. 30; NO 8; PP. 1228-1233; BIBL. 11 REF.Article

Method to reduce the sign bit extension in a multiplier that uses the modified booth algorithmROORDA, M.Electronics Letters. 1986, Vol 22, Num 20, pp 1061-1062, issn 0013-5194Article

Propriétés en charge d'amplificateurs microondes avec addition de puissance dans une charge communeZAENTSEV, V. V; MINKIN, M. A.Radiotehnika i èlektronika. 1984, Vol 29, Num 10, pp 1966-1970, issn 0033-8494Article

MOYENS D'AUGMENTER LE RENDEMENT DES SYSTEMES MULTICANAUX D'ADDITION-DIVISION DE PUISSANCE A LIGNES A MICROBANDESZAENTSEV VV.1981; IZV. VYSS. UCEBN. ZAVED., RADIOELEKTRON.; ISSN 0021-3470; SUN; DA. 1981; VOL. 24; NO 9; PP. 42-47; BIBL. 7 REF.Article

Pipelined carry look-ahead adderCRAWLEY, D. G; AMARATUNGA, G. A. J.Electronics Letters. 1986, Vol 22, Num 12, pp 661-662, issn 0013-5194Article

Luminescence-based molecular scale logic circuitsKUZNETZ, Olga; SPEISER, Shammai.Journal of luminescence. 2009, Vol 129, Num 12, pp 1415-1418, issn 0022-2313, 4 p.Conference Paper

Speculative Carry Generation With Prefix AdderCHOI, Youngmoon; SWARTZLANDER, Earl E.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 3, pp 321-326, issn 1063-8210, 6 p.Article

2-1 addition and related arithmetic operations with threshold logicVASSILIADIS, S; COTOFANA, S; BERTELS, K et al.IEEE transactions on computers. 1996, Vol 45, Num 9, pp 1062-1067, issn 0018-9340Article

An electrooptical adderARAZI, B.Proceedings of the IEEE. 1985, Vol 73, Num 1, pp 162-163, issn 0018-9219Article

A fast and area efficient complementary pass-transistor logic carry-skip adderSTROLLO, A. G. M; NAPOLI, E.International conference on microelectronic. 1997, pp 701-704, isbn 0-7803-3664-X, 2VolConference Paper

Modified delta-adder and delta-multiplier for multiplexingANASTASSOPOULOS, V; DELIYANNIS, T.International journal of electronics. 1984, Vol 57, Num 5, pp 719-727, issn 0020-7217Article

Estimating adders for a low density parity check decoderPHILLIPS, Braden J; KELLY, Daniel R; NG, Brian W et al.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 631302.1-631302.9, issn 0277-786X, isbn 0-8194-6392-2, 1VolConference Paper

Adder designs and analyses for quantum-dot cellular automataCHO, Heumpil; SWARTZLANDER, Earl E.IEEE transactions on nanotechnology. 2007, Vol 6, Num 3, pp 374-383, issn 1536-125X, 10 p.Article

A reduced-area scheme for carry-select addersTYAGI, A.IEEE transactions on computers. 1993, Vol 42, Num 10, pp 1163-1170, issn 0018-9340Article

Parity predictor for shifting-output addersVASSILIADIS, S; PUTRINO, M; SCHWARZ, E. M et al.Electronics Letters. 1989, Vol 25, Num 6, pp 422-424, issn 0013-5194, 3 p.Article

Méthode de construction de dispositifs triggers synchronisables à injectionSAMOJLOV, L. K; ROGOZOV, YU. I.Mikroèlektronika (Moskva). 1983, Vol 12, Num 6, pp 568-572, issn 0544-1269Article

LA RETENUE ANTICIPEE DANS LES CIRCUITS D'ADDITIONVABRE JP.1981; ONDE ELECTR.; ISSN 0030-2430; FRA; DA. 1981; VOL. 61; NO 1; PP. 57-64; ABS. ENGArticle

Improved 32-bit conditional sum adder for low-power high-speed applicationsCHENG, Kuo-Hsing; CHENG, Shun-Wen.Journal of information science and engineering. 2006, Vol 22, Num 4, pp 975-989, issn 1016-2364, 15 p.Article

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